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U631H64
SoftStore 8K x 8 nvSRAM
Features High-performance CMOS nonvolatile static RAM 8192 x 8 bits 25, 35 and 45 ns Access Times 12, 20 and 25 ns Output Enable Access Times Software STORE Initiation (STORE Cycle Time < 10 ms) Automatic STORE Timing 105 STORE cycles to EEPROM 10 years data retention in EEPROM Automatic RECALL on Power Up Software RECALL Initiation (RECALL Cycle Time < 20 s) Unlimited RECALL cycles from EEPROM Unlimited Read and Write to SRAM Single 5 V 10 % Operation Operating temperature ranges: 0 to 70 C -40 to 85 C QS 9000 Quality Standard ESD characterization according MIL STD 883C M3015.7-HBM (classification see IC Code Numbers) RoHS compliance and Pb- free Packages: PDIP28 (300 mil) SOP28 (330 mil) Description The U631H64 has two separate modes of operation: SRAM mode and nonvolatile mode. In SRAM mode, the memory operates as an ordinary static RAM. In nonvolatile operation, data is transferred in parallel from SRAM to EEPROM or from EEPROM to SRAM. In this mode SRAM functions are disabled. The U631H64 is a fast static RAM (25, 35, 45 ns), with a nonvolatile electrically erasable PROM (EEPROM) element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resides in EEPROM. Data transfers from the SRAM to the EEPROM (the STORE operation), or from the EEPROM to the SRAM (the RECALL operation) are initiated through software sequences. The U631H64 combines the high performance and ease of use of a fast SRAM with nonvolatile data integrity. Once a STORE cycle is initiated, further input or output are disabled until the cycle is completed. Because a sequence of addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence or the sequence will be aborted. Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times.
Pin Configuration
Pin Description
n.c. A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23
VCC W n.c. A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
Signal Name A0 - A12 DQ0 - DQ7 E G W VCC VSS
Signal Description Address Inputs Data In/Out Chip Enable Output Enable Write Enable Power Supply Voltage Ground
PDIP 22 SOP 21
20 19 18 17 16 15
Top View
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U631H64
Block Diagram
A5 Row Decoder A6 A7 A8 A9 A11 A12 DQ0 DQ1 Input Buffers DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 SRAM Array 128 Rows x 64 x 8 Columns
Store/ Recall Control
EEPROM Array 128 x (64 x 8) STORE RECALL VCC VSS
VCC
Column I/O Column Decoder
Software Detect
A0 - A12
A0 A1 A2 A3 A4 A10
G
E W
Truth Table for SRAM Operations Operating Mode Standby/not selected Internal Read Read Write * H or L Characteristics
All voltages are referenced to VSS = 0 V (ground). All characteristics are valid in the power supply voltage range and in the operating temperature range specified. Dynamic measurements are based on a rise and fall time of 5 ns, measured between 10 % and 90 % of VI, as well as input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V, with the exception of the tdis-times and ten-times, in which cases transition is measured 200 mV from steady-state voltage.
E H L L L
W
*
G
*
DQ0 - DQ7 High-Z High-Z Data Outputs Low-Z Data Inputs High-Z
H H L
H L
*
Absolute Maximum Ratinga Power Supply Voltage Input Voltage Output Voltage Power Dissipation Operating Temperature Storage Temperature C-Type K-Type
Symbol VCC VI VO PD Ta Tstg
Min. -0.5 -0.3 -0.3
Max. 7 VCC+0.5 VCC+0.5 1
Unit V V V W C C C
0 -40 -65
70 85 150
a: Stresses greater than those listed under Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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U631H64
Recommended Operation Conditions Power Supply Voltage Input Low Voltage Input High Voltage Symbol VCC VIL VIH -2 V at Pulse Width 10 ns permitted Conditions Min. 4.5 -0.3 2.2 Max. 5.5 0.8 VCC+0.3 Unit V V V
C-Type DC Characteristics Operating Supply Currentb Symbol ICC1 VCC VIL VIH tc tc tc Average Supply Current during STOREc ICC2 VCC E W VIL VIH VCC E tc tc tc Average Supply Current at tcR = 200 ns b (Cycling CMOS Input Levels) Standby Supply Currentd (Stable CMOS Input Levels) ICC3 VCC W VIL VIH VCC E VIL VIH Conditions Min. = 5.5 V = 0.8 V = 2.2 V = 25 ns = 35 ns = 45 ns = 5.5 V V CC-0.2 V V CC-0.2 V 0.2 V V CC-0.2 V = 5.5 V VIH = 25 ns = 35 ns = 45 ns = 5.5 V V CC-0.2 V 0.2 V V CC-0.2 V = 5.5 V V CC-0.2 V 0.2 V V CC-0.2 V 30 23 20 15 90 80 75 6 Max.
K-Type Unit Min. Max.
95 85 80 7
mA mA mA mA
Standby Supply Currentd (Cycling TTL Input Levels)
ICC(SB)1
34 27 23 15
mA mA mA mA
ICC(SB)
1
1
mA
b: ICC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. The current ICC1 is measured for WRITE/READ - ratio of 1/2. c: ICC2 is the average current requird for the duration of the STORE cycle (STORE Cycle Time). d: Bringing E VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION table. The current ICC(SB)1 is measured for WRITE/READ - ratio of 1/2.
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U631H64
C-Type DC Characteristics Symbol VCC IOH IOL VCC VOH VOL VCC High Low Output Leakage Current High at Three-State- Output Low at Three-State- Output IOHZ IOLZ IIH IIL VIH VIL VCC VOH VOL Conditions Min. Output High Voltage Output Low Voltage Output High Current Output Low Current Input Leakage Current VOH VOL IOH IOL = 4.5 V =-4 mA = 8 mA = 4.5 V = 2.4 V = 0.4 V = 5.5 V = 5.5 V = 0V = 5.5 V = 5.5 V = 0V 1 -1 -1 1 A A 1 -1 -1 1 A A 2.4 0.4 -4 8 8 Max. Min. 2.4 0.4 -4 Max. V V mA mA K-Type Unit
SRAM Memory Operations Symbol Alt. tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tELQX tGLQX tAXQX tELICCH tEHICCL IEC tcR ta(A) ta(E) ta(G) tdis(E) tdis(G) ten(E) ten(G) tv(A) tPU tPD 5 0 3 0 25 25 35 45 Unit Min. Max. Min. Max. Min. Max. 25 25 25 12 13 13 5 0 3 0 35 35 35 35 20 17 17 5 0 3 0 45 45 45 45 25 20 20 ns ns ns ns ns ns ns ns ns ns ns
No. 1 2 3 4 5 6 7 8 9
Switching Characteristics Read Cycle Read Cycle Timef Address Access Time to Data Validg Chip Enable Access Time to Data Valid Output Enable Access Time to Data Valid E HIGH to Output in High-Zh G HIGH to Output in High-Zh E LOW to Output in Low-Z G LOW to Output in Low-Z Output Hold Time after Addr. Changeg
10 Chip Enable to Power Activee 11 Chip Disable to Power Standby d, e
e: f: g: h:
Parameter guaranteed but not tested. Device is continuously selected with E and G both LOW. Address valid prior to or at the same time with E transition LOW. Measured 200 mV from steady state output voltage.
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U631H64
Read Cycle 1: Ai-controlled (during Read cycle: E = G = V IL, W = VIH)f
tcR
(1)
Ai DQi
Output Previous Data Valid tv(A) (9)
Address Valid ta(A) (2) Output Data Valid
Read Cycle 2: G-, E-controlled (during Read cycle: W = V IH)g
tcR
(1)
Ai E G DQi
Output High Impedance ACTIVE STANDBY
Address Valid ta(A) (2) ta(E) (3) ten(E) (7) ta(G) (4) ten(G) (8) tPU (10)
tPD (11) tdis(E) (5) tdis(G) (6) Output Data Valid
ICC
No. Switching Characteristics Write Cycle 12 Write Cycle Time 13 Write Pulse Width 14 Write Pulse Width Setup Time 15 Address Setup Time 16 Address Valid to End of Write 17 Chip Enable Setup Time 18 Chip Enable to End of Write 19 Data Setup Time to End of Write 20 Data Hold Time after End of Write 21 Address Hold after End of Write 22 W LOW to Output in High-Zh, i 23 W HIGH to Output in Low-Z
Symbol Alt. #1 Alt. #2 IEC
25
35
45
Unit
Min. Max. Min. Max. Min. Max.
tAVAV tWLWH
tAVAV
tcW tw(W)
25 20 20 0
35 30 30 0 30 30 30 18 0 0 10 13 5
45 35 35 0 35 35 35 20 0 0 15 5
ns ns ns ns ns ns ns ns ns ns ns ns
tWLEH tAVWL tAVWH tELWH tELEH tDVWH tWHDX tWHAX tWLQZ tWHQX tDVEH tEHDX tEHAX tAVEL
tsu(W) tsu(A)
tAVEH tsu(A-WH) 20 tsu(E) tw(E) tsu(D) th(D) th(A) tdis(W) ten(W) 5 20 20 12 0 0
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U631H64
Write Cycle #1: W-controlledj
tcW
(12)
Ai
tsu(E)
Address Valid
(17)
th(A) (21)
E W
tsu(A) tsu(A-WH) (16) tw(W) (13) tsu(D) 19 tdis(W) Previous Data Valid
(22)
DQi
Input
(15)
th(D) (20)
Input Data Valid ten(W) (23) High Impedance
DQi
Output
Write Cycle #2: E-controlledj
tcW
(12)
Ai E W DQi
Input tsu(A) (15)
Address Valid tw(E) (18)
th(A) (21)
tsu(W) (14) tsu(D) (19) th(D) (20)
Input Data Valid High Impedance
DQi
Output
undefined
L- to H-level
H- to L-level
i: j:
If W is LOW and when E goes LOW, the outputs remain in the high impedance state. E or W must be > VIH during address transitions.
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U631H64
Nonvolatile Memory Operations STORE Cycle Inhibit and Automatic Power Up RECALL Symbol Min. Alt. tRESTORE VSWITCH 4.0 IEC 650 4.5 s V Max. Unit
No.
24 Power Up RECALL Duration k, e Low Voltage Trigger Level
k: tRESTORE starts from the time VCC rises above VSWITCH.
STORE Cycle Inhibit and Automatic Up RECALL VCC 5.0 V VSWITCH
t STORE inhibit Power Up RECALL
(24)
tRESTORE
Software Mode Selection E L W H A12 - A0 (hex) 0000 1555 0AAA 1FFF 10F0 0F0F 0000 1555 0AAA 1FFF 10F0 0F0E Mode Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL I/O Output Data Output Data Output Data Output Data Output Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z Power Active Notes l, m l, m l, m l, m l, m l l, m l, m l, m l, m l, m l
ICC2 Active
L
H
The six consecutive addresses must be in order listed (0000, 1555, 0AAA, 1FFF, 10F0, 0F0F) for a Store cycle or (0000, 1555, 0AAA, 1FFF, 10F0, 0F0E) for a RECALL cycle. W must be high during all six consecutive cycles. See STORE cycle and RECALL cycle tables and diagrams for further details. The following six-address sequence is used for testing purposes and should not be used: 0000, 1555, 0AAA, 1FFF, 10F0, 139C. m: I/O state assumes that G VIL. Activation of nonvolatile cycles does not depend on the state of G.
l:
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U631H64
Symbol No. Software Controlled STORE/RECALL Cyclel, n 25 STORE/RECALL Initiation Time 26 Chip Enable to Output Inactive o 27 STORE Cycle Timep 28 RECALL Cycle Timeq 29 Address Setup to Chip Enable r 30 Chip Enable Pulse Width r, s 31 Chip Disable to Address Changer
Alt. IEC
25
35
45
Unit
Min. Max. Min. Max. Min. Max.
tAVAV tELQZ tELQXS tELQXR tAVELN tELEHN tEHAXN
tcR tdis(E)SR td(E)S td(E)R tsu(A)SR tw(E)SR th(A)SR
25 600 10 20 0 20 0
35 600 10 20 0 25 0
45 600 10 20 0 35 0
ns ns ms s ns ns ns
n: o: p: q: r: s:
The software sequence is clocked with E controlled READs. Once the software controlled STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs. Note that STORE cycles (but not RECALL) are aborted by VCC < VSWITCH (STORE inhibit). An automatic RECALL also takes place at power up, starting when VCC exceeds VSWITCH and takes tRESTORE. VCC must not drop below VSWITCH once it has been exceeded for the RECALL to function properly. Noise on the E pin may trigger multiple READ cycles from the same address and abort the address sequence. If the Chip Enable Pulse Width is less than ta(E) (see Read Cycle) but greater than or equal tw(E)SR, than the data may not be valid at the end of the low pulse, however the STORE or RECALL will still be initiated.
Software Controlled STORE/RECALL Cycler, s, t, u (E = HIGH after STORE initiation)
tcR (25) ADDRESS 6 tw(E)SR (31) th(A)SR
(30) (31)
tcR (25)
Ai E DQi
Output
ADDRESS 1 tw(E)SR tsu(A)SR (29) High Impedance
(30)
th(A)SR
tsu(A)SR
(29)
tdis(E) (5)
td(E)S (27) td(E)R (28) VALID tdis(E)SR (26)
VALID
Software Controlled STORE/RECALL Cycler, s, t, u (E = LOW after STORE initiation)
tcR (25)
Ai E
tsu(A)SR (29)
ADDRESS 1 tw(E)SR
(30) (31) th(A)SR (29)
ADDRESS 6 th(A)SR (31) td(E)S (27) td(E)R (28)
DQi
Output
tsu(A)SR
High Impedance
VALID
VALID tdis(E)SR (26)
W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW throughout. Addresses 1 through 6 are found in the mode selection table. Address 6 determines whether the U631H64 performs a STORE or RECALL. u: E must be used to clock in the address sequence for the Software controlled STORE and RECALL cycles.
t:
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U631H64
Test Configuration for Functional Check
5V
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12
VCC w
relevant test measurement
Input level according to the
VIH
DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
VIL
ment of all 8 output pins
Simultaneous measure-
DQ0
480
VO 30 pF v 255
E W G
VSS
v: In measurement of tdis-times and ten-times the capacitance is 5 pF. w: Between VCC and V SS must be connected a high frequency bypass capacitor 0.1 F to avoid disturbances.
Capacitancee Input Capacitance Output Capacitance
Conditions VCC VI f Ta = 5.0 V = VSS = 1 MHz = 25 C
Symbol CI CO
Min.
Max. 8 7
Unit pF pF
All pins not under test must be connected with ground by capacitors. Ordering Code Example Type ESD Class blank > 2000 V B > 1000 V Package D = PDIP28 (300 mil) S = SOP28 (330 mil) Type 1 S2 = SOP28 (330 mil) Type 2
x: on special request
U631H64
S
C
25 G1 Leadfree Option blank = Standard Package G1 = Leadfree Green Package x Access Time 25 = 25 ns 35 = 35 ns x 45 = 45 ns x
Operating Temperature Range C = 0 to 70 C K = -40 to 85 C
Device Marking (example) Product specification
ZMD U631H64SC 25 Z 0425 G1
Date of manufacture (The first 2 digits indicating the year, and the last 2 digits the calendar week.) Leadfree Green Package
Internal Code
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U631H64
Device Operation The U631H64 has two separate modes of operation: SRAM mode and nonvolatile mode. In SRAM mode, the memory operates as a standard fast static RAM. In nonvolatile mode, data is transferred from SRAM to EEPROM (the STORE operation) or from EEPROM to SRAM (the RECALL operation). In this mode SRAM functions are disabled. SRAM READ The U631H64 performs a READ cycle whenever E and G are LOW while W is HIGH. The address specified on pins A0 - A12 determines which of the 8192 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tcR. If the READ is initiated by E or G, the outputs will be valid at ta(E) or at ta(G), whichever is later. The data outputs will repeatedly respond to address changes within the tcR access time without the need for transition on any control input pins, and will remain valid until another address change or until E or G is brought HIGH or W is brought LOW. SRAM WRITE Software Nonvolatile RECALL A WRITE cycle is performed whenever E and W are LOW. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W goes HIGH at the end of the cycle. The data on pins DQ0 - 7 will be written into the memory if it is valid tsu(D) before the end of a W controlled WRITE or tsu(D) before the end of an E controlled WRITE. It is recommended that G is kept HIGH during the entire WRITE cycle to avoid data bus contention on the common I/O lines. If G is left LOW, internal circuitry will turn off the output buffers tdis(W) after W goes LOW. Noise Consideration The U631H64 is a high speed memory and therefore it must have a high frequency bypass capacitor of approximately 0.1 F connected between VCC and VSS using leads and traces that are as short as possible. As with all high speed CMOS ICs, normal carefull routing of power, ground and signals will help prevent noise problems. Software Nonvolatile STORE The U631H64 software controlled STORE cycle is initiated by executing sequential READ cycles from six specific address locations. By relying on READ cycles only, the U631H64 implements nonvolatile operation while remaining compatible with standard 8K x 8 SRAMs. During the STORE cycle, an erase of the previous nonvolatile data is first performed, followed by On power up, once VCC exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated. The voltage on the VCC pin must not drop below VSWITCH once it has risen above it in order for the RECALL to operate properly. A RECALL cycle of the EEPROM data into the SRAM is initiated with a sequence of READ operations in a manner similar to the STORE initiation. To initiate the RECALL cycle the following sequence of READ operations must be performed: 1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 0000 1555 0AAA 1FFF 10F0 0F0E (hex) (hex) (hex) (hex) (hex) (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate RECALL 1. 2. 3. 4. 5. 6. Read address Read address Read address Read address Read address Read address 0000 1555 0AAA 1FFF 10F0 0F0F (hex) (hex) (hex) (hex) (hex) (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate STORE parallel programming of all nonvolatile elements. Once a STORE cycle is initiated, further inputs and outputs are disabled until the cycle is completed. Because a sequence of addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence or the sequence will be aborted and no STORE or RECALL will take place. To initiate the STORE cycle the following READ sequence must be performed:
Once the sixth address in the sequence has been entered, the STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles are used in the sequence. It is not necessary that G is LOW for the sequence to be valid. After the tSTORE cycle time has been fulfilled, the SRAM will again be activated for READ and WRITE operation.
Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times. Automatic Power Up RECALL
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U631H64
Due to this automatic RECALL, SRAM operation cannot commence until tRESTORE after V CC exceeds VSWITCH. If the U631H64 is in a WRITE state at the end of power up RECALL, the SRAM data will be corrupted. To help avoid this situation, a 10 K resistor should be connected between W and VCC. Hardware Protection The U631H64 offers hardware protection against inadvertent STORE operation through VCC sense. For VCC < VSWITCH the software initiated STORE operation will be inhibited. Low Average Active Power The U631H64 has been designed to draw significantly less power when E is LOW (chip enabled) but the access cycle time is longer than 55 ns. When E is HIGH the chip consumes only standby current. The overall average current drawn by the part depends on the following items: 1. CMOS or TTL input levels 2. the time during which the chip is disabled (E HIGH) 3. the cycle time for accesses (E LOW) 4. the ratio of READs to WRITEs 5. the operating temperature 6. the VCC level
The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved.
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U631H64
LIFE SUPPORT POLICY ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ZMD product could create a situation where personal injury or death may occur. Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose.
LIMITED WARRANTY The information in this document has been carefully checked and is believed to be reliable. However Zentrum Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it. The information in this document describes the type of component and shall not be considered as assured characteristics. ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trademark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This document does not in any way extent ZMD's warranty on any product beyond that set forth in its standard terms and conditions of sale. ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both, presented in this publication at any time and without notice.
April 7, 2005
Zentrum Mikroelektronik Dresden AG Grenzstrae 28 * D-01109 Dresden * P. O. B. 80 01 34 * D-01101 Dresden * Germany Phone: +49 351 8822 306 * Fax: +49 351 8822 337 * Email: memory@zmd.de * http://www.zmd.de

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